Efficient AES implementations on ASICs and FPGAs
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Recommendations
- Implementation of the AES-128 on Virtex-5 FPGAs
- Architectural optimization for a 1. 82 Gbits/sec VLSI implementation of the AES Rijndael algorithm
- Single-chip FPGA implementation of the advanced encryption standard algorithm
- AES on FPGA from the Fastest to the Smallest
- Efficient VLSI architectures for the advanced encryption standard algorithm
Cited in
(26)- Looting the LUTs: FPGA optimization of AES and AES-like ciphers for authenticated encryption
- Efficient cryptography on the RISC-V architecture
- Intel’s New AES Instructions for Enhanced Performance and Security
- Implementation of the AES-128 on Virtex-5 FPGAs
- Ultra-Lightweight Implementations for Smart Devices – Security for 1000 Gate Equivalents
- Integrating FPGA/ASIC into cryptographic storage systems to avoid re-encryption
- Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture
- An ASIC implementation of the AES S-boxes
- A compact Rijndael hardware architecture with S-Box optimization
- A comparative study of performance of AES final candidates using FPGAs
- Architectures and VLSI implementations of the AES-Proposal Rijndael
- PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC
- Single-chip FPGA implementation of the advanced encryption standard algorithm
- Architectural optimization for a 1. 82 Gbits/sec VLSI implementation of the AES Rijndael algorithm
- Efficient Vector Implementations of AES-Based Designs: A Case Study and New Implemenations for Grøstl
- Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs
- Very Short Critical Path Implementation of AES with Direct Logic Gates
- Programmable cellular automata (PCA) based advanced encryption standard (AES) hardware architecture
- Efficient VLSI architectures for the advanced encryption standard algorithm
- Bitslice Implementation of AES
- A Versatile Pipelined Hardware Implementation for Encryption and Decryption Using Advanced Encryption Standard
- Chai-Tea, Cryptographic Hardware Implementations of xTEA
- Ensuring Fast Implementations of Symmetric Ciphers on the Intel Pentium 4 and Beyond
- Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA
- Resource efficient implementation of T-boxes in AES on virtex-5 FPGA
- Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard
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