An ASIC implementation of the AES S-boxes
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Cited in
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- A Very Compact “Perfectly Masked” S-Box for AES
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- Using Normal Bases for Compact Hardware Implementations of the AES S-Box
- Practical Attacks on Masked Hardware
- AES side-channel countermeasure using random tower field constructions
- Hardware design and analysis of block cipher components
- An optimized S-Box circuit architecture for low power AES design
- A compact Rijndael hardware architecture with S-Box optimization
- Architectures and VLSI implementations of the AES-Proposal Rijndael
- Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs
- Very Short Critical Path Implementation of AES with Direct Logic Gates
- Topics in Cryptology – CT-RSA 2005
- Secure hardware implementation of nonlinear functions in the presence of glitches
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