Secure hardware implementation of nonlinear functions in the presence of glitches
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Recommendations
- Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
- Threshold Implementations Against Side-Channel Attacks and Glitches
- On the simplicity of converting leakages from multivariate to univariate. (Case study of a glitch-resistant masking scheme)
- Formal verification of masked hardware implementations in the presence of glitches
- Higher-order glitches free implementation of the AES using secure multi-party computation protocols
Cites work
- scientific article; zbMATH DE number 1979284 (Why is no real title available?)
- scientific article; zbMATH DE number 1979285 (Why is no real title available?)
- scientific article; zbMATH DE number 2079921 (Why is no real title available?)
- scientific article; zbMATH DE number 1759268 (Why is no real title available?)
- scientific article; zbMATH DE number 1878339 (Why is no real title available?)
- scientific article; zbMATH DE number 1418307 (Why is no real title available?)
- A Very Compact S-Box for AES
- Advanced Encryption Standard – AES
- Advances in Cryptology - CRYPTO 2003
- Block Ciphers Implementations Provably Secure Against Second Order Side Channel Analysis
- Cryptographic Hardware and Embedded Systems - CHES 2004
- DPA Leakage Models for CMOS Logic Circuits
- Fast Software Encryption
- Fast Software Encryption
- How to share a secret
- Mutual Information Analysis: How, When and Why?
- PRESENT: An Ultra-Lightweight Block Cipher
- Power Analysis Attacks
- Private Circuits II: Keeping Secrets in Tamperable Circuits
- Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
- Selected Areas in Cryptography
- Side-channel resistant crypto for less than 2,300 GE
- The world is not enough: another look on second-order DPA
- Threshold Implementations Against Side-Channel Attacks and Glitches
- Topics in Cryptology – CT-RSA 2005
- Topics in Cryptology – CT-RSA 2006
- Towards sound approaches to counteract power-analysis attacks
Cited in
(52)- How fast can higher-order masking be in software?
- Monomial evaluation of polynomial functions protected by threshold implementations -- with an illustration on AES -- extended version
- From substitution box to threshold
- Towards tight random probing security
- Arithmetic Addition over Boolean Masking
- \textsc{Ascon} v1.2: lightweight authenticated encryption and hashing
- Threshold implementation in software. Case study of PRESENT
- Universal hashing based on field multiplication and (near-)MDS matrices
- Boosting higher-order correlation attacks by dimensionality reduction
- A further study on bridge structures and constructing bijective S-boxes for low-latency masking
- Bridging the gap: advanced tools for side-channel leakage estimation beyond Gaussian templates and histograms
- Uniform first-order threshold implementations
- \texttt{POLKA}: towards leakage-resistant post-quantum CCA-secure public key encryption
- Taylor expansion of maximum likelihood attacks for masked and shuffled implementations
- A methodology for the characterisation of leakages in combinatorial logic
- Threshold implementations of small S-boxes
- Enabling 3-share threshold implementations for all 4-bit S-boxes
- Affine equivalence and its application to tightening threshold implementations
- On masked Galois-field multiplication for authenticated encryption resistant to side channel analysis
- Leakage resilient value comparison with application to message authentication
- Making masking security proofs concrete (or how to evaluate the security of any leaking device), extended version
- Accelerating SLH-DSA by two orders of magnitude with a single hash unit
- Towards sound fresh re-keying with hard (physical) learning problems
- Side-channel analysis protection and low-latency in action -- case study of PRINCE and Midori
- SILVER -- statistical independence and leakage verification
- Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
- Handcrafting: improving automated masking in hardware with manual optimizations
- A first-order SCA resistant AES without fresh randomness
- AES side-channel countermeasure using random tower field constructions
- ParTI -- towards combined hardware countermeasures against side-channel and fault-injection attacks
- A small GIFT-COFB: lightweight bit-serial architectures
- Higher-order glitch resistant implementation of the PRESENT S-box
- Effective and efficient masking with low noise using small-Mersenne-prime ciphers
- On the simplicity of converting leakages from multivariate to univariate. (Case study of a glitch-resistant masking scheme)
- Mode-level vs. implementation-level physical security in symmetric cryptography. A practical guide through the leakage-resistance jungle
- Homomorphic \(\mathrm {SIM}^2\)D operations: single instruction much more data
- Formal verification of masked hardware implementations in the presence of glitches
- Algebraic decomposition for probing security
- Spin me right round rotational symmetry for FPGA-specific AES: extended version
- Connecting leakage-resilient secret sharing to practice: scaling trends and physical dependencies of prime field masking
- Resilient uniformity: applying resiliency in masking
- Hiding higher-order side-channel leakage. Randomizing cryptographic implementations in reconfigurable hardware
- SAND: an AND-RX Feistel lightweight block cipher supporting S-box-based security evaluations
- Parallel Implementations of Masking Schemes and the Bounded Moment Leakage Model
- Complementing Feistel ciphers
- Codes for side-channel attacks and protections
- Redefining the transparency order
- Unknown-input attacks in the parallel setting: improving the security of the CHES 2012 leakage-resilient PRF
- Improving first-order threshold implementations of \textsf{SKINNY}
- Succinct Diophantine-satisfiability arguments
- Threshold Implementations Against Side-Channel Attacks and Glitches
- Constructions of S-boxes with uniform sharing
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