Topics in Cryptology – CT-RSA 2005
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Publication:5710844
DOI10.1007/b105222zbMath1079.94561OpenAlexW2476332689MaRDI QIDQ5710844
Thomas Popp, Stefan Mangard, Berndt M. Gammel
Publication date: 8 December 2005
Published in: Lecture Notes in Computer Science (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/b105222
Related Items (27)
Monomial evaluation of polynomial functions protected by threshold implementations -- with an illustration on AES -- extended version ⋮ Towards tight random probing security ⋮ Homomorphic \(\mathrm {SIM}^2\)D operations: single instruction much more data ⋮ Enabling 3-Share Threshold Implementations for all 4-Bit S-Boxes ⋮ Masking Tables—An Underestimated Security Risk ⋮ Higher-Order Glitch Resistant Implementation of the PRESENT S-Box ⋮ Masking and leakage-resilient primitives: one, the other(s) or both? ⋮ Effective and efficient masking with low noise using small-Mersenne-prime ciphers ⋮ Handcrafting: improving automated masking in hardware with manual optimizations ⋮ \texttt{POLKA}: towards leakage-resistant post-quantum CCA-secure public key encryption ⋮ Unknown-Input Attacks in the Parallel Setting: Improving the Security of the CHES 2012 Leakage-Resilient PRF ⋮ Higher-order masking scheme for Trivium hardware implementation ⋮ Bridging the gap: advanced tools for side-channel leakage estimation beyond Gaussian templates and histograms ⋮ Learning with physical rounding for linear and quadratic leakage functions ⋮ An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order ⋮ Secure hardware implementation of nonlinear functions in the presence of glitches ⋮ Parallel Implementations of Masking Schemes and the Bounded Moment Leakage Model ⋮ Codes for Side-Channel Attacks and Protections ⋮ Making masking security proofs concrete (or how to evaluate the security of any leaking device), extended version ⋮ Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches ⋮ Polynomial Evaluation and Side Channel Analysis ⋮ Design of a Differential Power Analysis Resistant Masked AES S-Box ⋮ Practical Attacks on Masked Hardware ⋮ Fault Analysis Attack against an AES Prototype Chip Using RSL ⋮ Towards Sound Fresh Re-keying with Hard (Physical) Learning Problems ⋮ ParTI – Towards Combined Hardware Countermeasures Against Side-Channel and Fault-Injection Attacks ⋮ Mode-level vs. implementation-level physical security in symmetric cryptography. A practical guide through the leakage-resistance jungle
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