ParTI -- towards combined hardware countermeasures against side-channel and fault-injection attacks
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Publication:2829219
DOI10.1007/978-3-662-53008-5_11zbMATH Open1391.94796OpenAlexW2494396870MaRDI QIDQ2829219FDOQ2829219
Amir Moradi, Tim Güneysu, Tobias M. Schneider
Publication date: 27 October 2016
Published in: Advances in Cryptology – CRYPTO 2016 (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-662-53008-5_11
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- My gadget just cares for me -- how NINA can prove security against combined attacks
Cites Work
- Algebraic Codes for Data Transmission
- Wire-Tap Codes as Side-Channel Countermeasure
- Title not available (Why is that?)
- Title not available (Why is that?)
- Title not available (Why is that?)
- PRESENT: An Ultra-Lightweight Block Cipher
- The LED Block Cipher
- Higher-Order Glitches Free Implementation of the AES Using Secure Multi-party Computation Protocols
- Secure hardware implementation of nonlinear functions in the presence of glitches
- Threshold Implementations of All 3 ×3 and 4 ×4 S-Boxes
- Threshold implementations of small S-boxes
- Threshold Implementations Against Side-Channel Attacks and Glitches
- Topics in Cryptology – CT-RSA 2005
- Side-channel resistant crypto for less than 2,300 GE
- Pushing the Limits: A Very Compact and a Threshold Implementation of AES
- Consolidating Masking Schemes
- A More Efficient AES Threshold Implementation
- Assessment of hiding the higher-order leakages in hardware. What are the achievements versus overheads?
- Leakage assessment methodology. A clear roadmap for side-channel evaluations
- Higher-Order Threshold Implementations
- Infective Computation and Dummy Rounds: Fault Protection for Block Ciphers without Check-before-Output
- Side-Channel Analysis Protection and Low-Latency in Action
- Arithmetic Addition over Boolean Masking
- Affine Equivalence and Its Application to Tightening Threshold Implementations
- Higher-Order Glitch Resistant Implementation of the PRESENT S-Box
Cited In (12)
- Differential fault attack on lightweight block cipher PIPO
- Custom instruction support for modular defense against side-channel and fault attacks
- Combined fault and leakage resilience: composability, constructions and compiler
- Light but tight: lightweight composition of serialized S-boxes with diffusion layers for strong ciphers
- Statistical properties of side-channel and fault injection attacks using coding theory
- Quantitative fault injection analysis
- Trade-offs in protecting \textsc{Keccak} against combined side-channel and fault attacks
- The random fault model
- Feeding Two Cats with One Bowl: On Designing a Fault and Side-Channel Resistant Software Encoding Scheme
- \textsc{Friet}: an authenticated encryption scheme with built-in fault detection
- Fault template attacks on block ciphers exploiting fault propagation
- Divided we stand, united we fall: security analysis of some SCA+SIFA countermeasures against SCA-enhanced fault template attacks
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