ParTI -- towards combined hardware countermeasures against side-channel and fault-injection attacks
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Publication:2829219
DOI10.1007/978-3-662-53008-5_11zbMATH Open1391.94796OpenAlexW2494396870MaRDI QIDQ2829219FDOQ2829219
Authors: Amir Moradi, Tim Güneysu, Tobias M. Schneider
Publication date: 27 October 2016
Published in: Advances in Cryptology – CRYPTO 2016 (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-662-53008-5_11
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Cites Work
- Algebraic Codes for Data Transmission
- Wire-tap codes as side-channel countermeasure
- Title not available (Why is that?)
- Title not available (Why is that?)
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- PRESENT: An Ultra-Lightweight Block Cipher
- The LED block cipher
- Higher-order glitches free implementation of the AES using secure multi-party computation protocols
- Secure hardware implementation of nonlinear functions in the presence of glitches
- Threshold implementations of all \(3 \times 3\) and \(4 \times 4\) S-boxes
- Threshold implementations of small S-boxes
- Threshold Implementations Against Side-Channel Attacks and Glitches
- Topics in Cryptology – CT-RSA 2005
- Side-channel resistant crypto for less than 2,300 GE
- Pushing the limits: a very compact and a threshold implementation of AES
- Consolidating masking schemes
- A more efficient AES threshold implementation
- Assessment of hiding the higher-order leakages in hardware. What are the achievements versus overheads?
- Leakage assessment methodology. A clear roadmap for side-channel evaluations
- Higher-Order Threshold Implementations
- Infective computation and dummy rounds: fault protection for block ciphers without check-before-output
- Side-channel analysis protection and low-latency in action -- case study of PRINCE and Midori
- Arithmetic Addition over Boolean Masking
- Affine equivalence and its application to tightening threshold implementations
- Higher-order glitch resistant implementation of the PRESENT S-box
Cited In (16)
- Differential fault attack on lightweight block cipher PIPO
- Custom instruction support for modular defense against side-channel and fault attacks
- Combined fault and leakage resilience: composability, constructions and compiler
- Light but tight: lightweight composition of serialized S-boxes with diffusion layers for strong ciphers
- Statistical properties of side-channel and fault injection attacks using coding theory
- The first thorough side-channel hardware Trojan
- Feeding two cats with one bowl: on designing a fault and side-channel resistant software encoding scheme
- Quantitative fault injection analysis
- Trade-offs in protecting \textsc{Keccak} against combined side-channel and fault attacks
- The random fault model
- \textsc{Friet}: an authenticated encryption scheme with built-in fault detection
- Fault template attacks on block ciphers exploiting fault propagation
- CAPA: the spirit of beaver against physical attacks
- My gadget just cares for me -- how NINA can prove security against combined attacks
- Divided we stand, united we fall: security analysis of some SCA+SIFA countermeasures against SCA-enhanced fault template attacks
- Statistical ineffective fault attacks on masked AES with fault countermeasures
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