Custom instruction support for modular defense against side-channel and fault attacks
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Publication:2106699
DOI10.1007/978-3-030-68773-1_11zbMATH Open1504.94159OpenAlexW3110984563MaRDI QIDQ2106699FDOQ2106699
Authors: Pantea Kiaei, Darius Mercadier, Pierre-Évariste Dagand, Karine Heydemann, Partrick Schaumont 
Publication date: 16 December 2022
Full work available at URL: https://doi.org/10.1007/978-3-030-68773-1_11
Recommendations
- Lightweight fault attack resistance in software using intra-instruction redundancy
- ParTI -- towards combined hardware countermeasures against side-channel and fault-injection attacks
- A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
- Trace-based schedulability analysis to enhance passive side-channel attack resilience of embedded software
- Preventing fault attacks using fault randomization with a case study on AES
Cites Work
- GitHub
- Secure Multiplication for Bitslice Higher-Order Masking: Optimisation and Comparison
- Randomness complexity of private circuits for multiplication
- Advances in Cryptology - CRYPTO 2003
- Cryptographic Hardware and Embedded Systems - CHES 2004
- A fast new DES implementation in software
- A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
- Bitslice Implementation of AES
- My gadget just cares for me -- how NINA can prove security against combined attacks
- Horizontal side-channel attacks and countermeasures on the ISW masking scheme
- Title not available (Why is that?)
- Very High Order Masking: Efficient Implementation and Security Evaluation
- Parallel Implementations of Masking Schemes and the Bounded Moment Leakage Model
- CAPA: the spirit of beaver against physical attacks
- Leakage assessment methodology. A clear roadmap for side-channel evaluations
- Lightweight fault attack resistance in software using intra-instruction redundancy
- Faster and Timing-Attack Resistant AES-GCM
- A Fast and Cache-Timing Resistant Implementation of the AES
- Tight private circuits: achieving probing security with the least refreshing
- ParTI -- towards combined hardware countermeasures against side-channel and fault-injection attacks
- Vectorizing Higher-Order Masking
- Using Virtual Secure Circuit to Protect Embedded Software from Side-Channel Attacks
Cited In (7)
- Characterizing and Exploiting Small-Value Memory Instructions
- Feeding two cats with one bowl: on designing a fault and side-channel resistant software encoding scheme
- Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors
- A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
- Trace-based schedulability analysis to enhance passive side-channel attack resilience of embedded software
- Lightweight fault attack resistance in software using intra-instruction redundancy
- A multiple-fault injection attack by adaptive timing control under black-box conditions and a countermeasure
Uses Software
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