A Fast and Cache-Timing Resistant Implementation of the AES
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Publication:5458940
DOI10.1007/978-3-540-79263-5_12zbMATH Open1153.68373OpenAlexW1490070390MaRDI QIDQ5458940FDOQ5458940
Authors: Robert Könighofer
Publication date: 24 April 2008
Published in: Topics in Cryptology – CT-RSA 2008 (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-540-79263-5_12
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Cites Work
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- A Bit-Slice Implementation of the Whirlpool Hash Function
- Montgomery’s Trick and Fast Implementation of Masked AES
- Custom instruction support for modular defense against side-channel and fault attacks
- Efficient cache attacks on AES, and countermeasures
- Efficient Vector Implementations of AES-Based Designs: A Case Study and New Implemenations for Grøstl
- Lightweight cryptography for the cloud: exploit the power of bitslice implementation
- Accelerating AES with Vector Permute Instructions
- Faster and Timing-Attack Resistant AES-GCM
- Ensuring Fast Implementations of Symmetric Ciphers on the Intel Pentium 4 and Beyond
- Fast Oblivious AES A Dedicated Application of the MiniMac Protocol
- New AES Software Speed Records
- Vectorizing higher-order masking
- Very Short Critical Path Implementation of AES with Direct Logic Gates
- An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order
- All the AES you need on Cortex-M3 and M4
- Bitslice Implementation of AES
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