All the AES you need on Cortex-M3 and M4
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Publication:1698628
DOI10.1007/978-3-319-69453-5_10zbMATH Open1412.94209OpenAlexW2574539584MaRDI QIDQ1698628FDOQ1698628
Authors: Peter Schwabe, Ko Stoffelen 
Publication date: 16 February 2018
Full work available at URL: http://hdl.handle.net/2066/178459
Recommendations
Cites Work
- Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems
- Title not available (Why is that?)
- A Very Compact S-Box for AES
- Advances in Cryptology - CRYPTO 2003
- A fast new DES implementation in software
- Efficient cache attacks on AES, and countermeasures
- Topics in Cryptology – CT-RSA 2006
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- How fast can higher-order masking be in software?
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- Faster and Timing-Attack Resistant AES-GCM
- Accelerating AES with Vector Permute Instructions
- A Fast and Cache-Timing Resistant Implementation of the AES
- New AES Software Speed Records
Cited In (16)
- SPEEDY on Cortex-M3: efficient software implementation of SPEEDY on ARM Cortex-M3
- AES smaller than S-box
- Faster and Timing-Attack Resistant AES-GCM
- Thinking outside the superbox
- Provable secure software masking in the real-world
- AES Software Implementations on ARM7TDMI
- Parallel verification of serial MAC and AE modes
- Vectorizing higher-order masking
- Boosting AES Performance on a Tiny Processor Core
- Fast first-order masked NTTRU
- All the HIGHT you need on Cortex-M4
- Fast AES implementation using ARMv8 ASIMD without cryptography extension
- FACE-LIGHT: fast AES-CTR mode encryption for low-end microcontrollers
- Side-channel attacks meet secure network protocols
- Tornado: automatic generation of probing-secure masked bitsliced implementations
- Implementing GCM on ARMv8
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