Boosting AES Performance on a Tiny Processor Core

DOI10.1007/978-3-540-79263-5_11zbMATH Open1153.68375OpenAlexW1496045316MaRDI QIDQ5458939FDOQ5458939

Stefan Tillich, Christoph Herbst

Publication date: 24 April 2008

Published in: Topics in Cryptology – CT-RSA 2008 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-79263-5_11

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• scientific article; zbMATH DE number 1979282

zbMATH Keywords

hardware-software codesignAdvanced Encryption Standard8-bit microcontrollerinstruction set extensionsAVR architecture

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

Cites Work

• Title not available (Why is that?)
• A Very Compact S-Box for AES
• VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors

Cited In (4)

• Intel’s New AES Instructions for Enhanced Performance and Security
• Implementation of Symmetric Algorithms on a Synthesizable 8-Bit Microcontroller Targeting Passive RFID Tags
• Title not available (Why is that?)
• A More Compact AES

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