| Publication | Date of Publication | Type |
|---|
| Energy consumption of protected cryptographic hardware cores. An experimental study | 2023-11-16 | Paper |
| SILVER -- statistical independence and leakage verification | 2023-03-21 | Paper |
| Impeccable Circuits | 2020-10-02 | Paper |
| A first-order SCA resistant AES without fresh randomness | 2020-07-20 | Paper |
| Threshold implementation in software. Case study of PRESENT | 2020-07-20 | Paper |
| Bit-sliding: a generic technique for bit-serial implementations of SPN-based primitives. Applications to AES, PRESENT and SKINNY | 2020-06-24 | Paper |
| Spin me right round rotational symmetry for FPGA-specific AES: extended version | 2020-06-15 | Paper |
| Improved side-channel analysis attacks on Xilinx bitstream encryption of 5, 6, and 7 series | 2019-12-05 | Paper |
| Bitstream Fault Injections (BiFI)–Automated Fault Attacks Against SRAM-Based FPGAs | 2018-06-27 | Paper |
| GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs | 2018-06-27 | Paper |
| White-box cryptography in the gray box | 2018-05-09 | Paper |
| The first thorough side-channel hardware Trojan | 2018-04-06 | Paper |
| Bridging the gap: advanced tools for side-channel leakage estimation beyond Gaussian templates and histograms | 2018-02-16 | Paper |
| Assessment of hiding the higher-order leakages in hardware. What are the achievements versus overheads? | 2018-02-14 | Paper |
| Leakage assessment methodology. A clear roadmap for side-channel evaluations | 2018-02-14 | Paper |
| Strong 8-bit sboxes with efficient masking in hardware | 2018-02-14 | Paper |
| One Attack to Rule Them All: Collision Timing Attack versus 42 AES ASIC Cores | 2017-07-12 | Paper |
| Hiding higher-order side-channel leakage. Randomizing cryptographic implementations in reconfigurable hardware | 2017-04-12 | Paper |
| Side-channel analysis protection and low-latency in action -- case study of PRINCE and Midori | 2017-02-01 | Paper |
| The SKINNY Family of Block Ciphers and Its Low-Latency Variant MANTIS | 2016-10-27 | Paper |
| ParTI -- towards combined hardware countermeasures against side-channel and fault-injection attacks | 2016-10-27 | Paper |
| Affine equivalence and its application to tightening threshold implementations | 2016-05-19 | Paper |
| Arithmetic Addition over Boolean Masking | 2016-03-10 | Paper |
| Full-size high-security ECC implementation on MSP430 microcontrollers | 2015-09-17 | Paper |
| Wire-tap codes as side-channel countermeasure | 2015-09-10 | Paper |
| Early propagation and imbalanced routing, how to diminish in FPGAs | 2015-07-21 | Paper |
| Comprehensive evaluation of AES dual ciphers as a side-channel countermeasure | 2014-09-29 | Paper |
| Detecting hidden leakages | 2014-07-07 | Paper |
| On the simplicity of converting leakages from multivariate to univariate. (Case study of a glitch-resistant masking scheme) | 2013-10-10 | Paper |
| Side-channel resistant crypto for less than 2,300 GE | 2012-01-18 | Paper |
| Generic Side-Channel Countermeasures for Reconfigurable Devices | 2011-10-07 | Paper |
| Pushing the limits: a very compact and a threshold implementation of AES | 2011-05-27 | Paper |
| Correlation-enhanced power analysis collision attack | 2010-08-17 | Paper |
| Practical power analysis attacks on software implementations of McEliece | 2010-06-17 | Paper |
| On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices | 2009-05-20 | Paper |
| Dual-rail transition logic: A logic style for counteracting power analysis attacks | 2009-03-20 | Paper |
| On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoq Code Hopping Scheme | 2009-02-10 | Paper |
