Side-Channel Analysis Protection and Low-Latency in Action
From MaRDI portal
Publication:2958135
DOI10.1007/978-3-662-53887-6_19zbMath1404.94099OpenAlexW2556763991MaRDI QIDQ2958135
Publication date: 1 February 2017
Published in: Advances in Cryptology – ASIACRYPT 2016 (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-662-53887-6_19
Related Items (4)
Succinct Diophantine-satisfiability arguments ⋮ SILVER -- statistical independence and leakage verification ⋮ Cryptanalysis of masked ciphers: a not so random idea ⋮ ParTI – Towards Combined Hardware Countermeasures Against Side-Channel and Fault-Injection Attacks
Uses Software
Cites Work
- Unnamed Item
- Secure hardware implementation of nonlinear functions in the presence of glitches
- Side-channel resistant crypto for less than 2,300 GE
- Threshold implementations of small S-boxes
- Assessment of hiding the higher-order leakages in hardware. What are the achievements versus overheads?
- Leakage assessment methodology. A clear roadmap for side-channel evaluations
- Towards easy leakage certification
- Improved Power Analysis on Unrolled Architecture and Its Application to PRINCE Block Cipher
- Midori: A Block Cipher for Low Energy
- Exploring Energy Efficiency of Lightweight Block Ciphers
- Power Analysis of Atmel CryptoMemory – Recovering Keys from Secure EEPROMs
- Higher-Order Threshold Implementations
- Pushing the Limits: A Very Compact and a Threshold Implementation of AES
- How to Protect DES Against Exhaustive Key Search
- PRESENT: An Ultra-Lightweight Block Cipher
- PRINTcipher: A Block Cipher for IC-Printing
- On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoq Code Hopping Scheme
- Threshold Implementations of All 3 ×3 and 4 ×4 S-Boxes
- Low-Latency Encryption – Is “Lightweight = Light + Wait”?
- PRINCE – A Low-Latency Block Cipher for Pervasive Computing Applications
- A More Efficient AES Threshold Implementation
- Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks
- Power Analysis Attacks
- Early Propagation and Imbalanced Routing, How to Diminish in FPGAs
- Cryptographic Hardware and Embedded Systems - CHES 2004
This page was built for publication: Side-Channel Analysis Protection and Low-Latency in Action
