Early propagation and imbalanced routing, how to diminish in FPGAs

DOI10.1007/978-3-662-44709-3_33zbMATH Open1383.94034OpenAlexW2176568615MaRDI QIDQ5265096FDOQ5265096

Authors: Amir Moradi, Vincent Immler 

Publication date: 21 July 2015

Published in: Advanced Information Systems Engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-662-44709-3_33

Recommendations

• QRL: a high performance quadruple-rail logic for resisting DPA on FPGA implementations
• Practical Attacks on Masked Hardware
• Generic Side-Channel Countermeasures for Reconfigurable Devices
• An interleaved EPE-immune PA-DPL structure for resisting concentrated EM side channel attacks on FPGA implementation
• Cryptographic Hardware and Embedded Systems - CHES 2004

Mathematics Subject Classification ID

Cryptography (94A60)

Cited In (4)

• An interleaved EPE-immune PA-DPL structure for resisting concentrated EM side channel attacks on FPGA implementation
• QRL: a high performance quadruple-rail logic for resisting DPA on FPGA implementations
• Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks
• Side-channel analysis protection and low-latency in action -- case study of PRINCE and Midori

This page was built for publication: Early propagation and imbalanced routing, how to diminish in FPGAs

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5265096)