An interleaved EPE-immune PA-DPL structure for resisting concentrated EM side channel attacks on FPGA implementation

DOI10.1007/978-3-642-29912-4_4zbMATH Open1352.94039OpenAlexW1592082951MaRDI QIDQ4905042FDOQ4905042

Authors: Wei He, Eduardo de la Torre, Teresa Riesgo 

Publication date: 14 February 2013

Published in: Constructive Side-Channel Analysis and Secure Design (Search for Journal in Brave)

Full work available at URL: http://oa.upm.es/19201/

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zbMATH Keywords

FPGAPIPLUTconcentrated em attackdual-coreinterleaved placementPA-DPLrouting conflict

Mathematics Subject Classification ID

Cryptography (94A60)

Cited In (2)

• QRL: a high performance quadruple-rail logic for resisting DPA on FPGA implementations
• Early propagation and imbalanced routing, how to diminish in FPGAs

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