QRL: a high performance quadruple-rail logic for resisting DPA on FPGA implementations

DOI10.1007/978-3-319-29814-6_15MaRDI QIDQ2801768zbMATH OpenOpenAlexFDO

Authors Chenyang Tu, Jian Zhou, Neng Gao, Zeyi Liu, Yuan Ma, Zongbin Liu

Publication date 21 April 2016

Published in Information and Communications Security (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-319-29814-6_15

zbMATH Keywords

FPGApower analysishigh performancedual-rail precharge logic (DPL)quadruple-rail

Mathematics Subject Classification ID

Cryptography (94A60)

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Cites work

• scientific article; zbMATH DE number 1418307 (Why is no real title available?)
• Advances in Cryptology - CRYPTO 2003
• An interleaved EPE-immune PA-DPL structure for resisting concentrated EM side channel attacks on FPGA implementation
• Cryptographic Hardware and Embedded Systems - CHES 2004

Cited in

(3)

• An interleaved EPE-immune PA-DPL structure for resisting concentrated EM side channel attacks on FPGA implementation
• Early propagation and imbalanced routing, how to diminish in FPGAs
• Dual-rail transition logic: A logic style for counteracting power analysis attacks

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