Hiding higher-order side-channel leakage. Randomizing cryptographic implementations in reconfigurable hardware
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Publication:2975801
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Cites work
- scientific article; zbMATH DE number 1951616 (Why is no real title available?)
- scientific article; zbMATH DE number 1979273 (Why is no real title available?)
- scientific article; zbMATH DE number 1418307 (Why is no real title available?)
- A white-box DES implementation for DRM applications
- Affine equivalence and its application to tightening threshold implementations
- Assessment of hiding the higher-order leakages in hardware. What are the achievements versus overheads?
- Comprehensive evaluation of AES dual ciphers as a side-channel countermeasure
- Consolidating masking schemes
- Higher-Order Threshold Implementations
- Leakage assessment methodology. A clear roadmap for side-channel evaluations
- PRESENT: An Ultra-Lightweight Block Cipher
- Power Analysis Attacks
- Secure hardware implementation of nonlinear functions in the presence of glitches
- Shuffling against side-channel attacks: a comprehensive study with cautionary note
- Side-channel resistant crypto for less than 2,300 GE
- Threshold Implementations Against Side-Channel Attacks and Glitches
- Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems
- Uniform first-order threshold implementations
- White-box security notions for symmetric encryption schemes
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