Hiding higher-order side-channel leakage. Randomizing cryptographic implementations in reconfigurable hardware

DOI10.1007/978-3-319-52153-4_8zbMATH Open1383.94042OpenAlexW2567810792MaRDI QIDQ2975801FDOQ2975801

Authors: Pascal Sasdrich, Amir Moradi, Tim Güneysu 

Publication date: 12 April 2017

Published in: Topics in Cryptology – CT-RSA 2017 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-319-52153-4_8

Recommendations

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Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

Cites Work

• Comprehensive evaluation of AES dual ciphers as a side-channel countermeasure
• Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems
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• PRESENT: An Ultra-Lightweight Block Cipher
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• Secure hardware implementation of nonlinear functions in the presence of glitches
• Power Analysis Attacks
• Threshold Implementations Against Side-Channel Attacks and Glitches
• Side-channel resistant crypto for less than 2,300 GE
• A white-box DES implementation for DRM applications
• Consolidating masking schemes
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• Shuffling against side-channel attacks: a comprehensive study with cautionary note
• Assessment of hiding the higher-order leakages in hardware. What are the achievements versus overheads?
• Leakage assessment methodology. A clear roadmap for side-channel evaluations
• Uniform first-order threshold implementations
• Higher-Order Threshold Implementations
• White-box security notions for symmetric encryption schemes
• Affine equivalence and its application to tightening threshold implementations

Cited In (3)

• Generic Side-Channel Countermeasures for Reconfigurable Devices
• Assessment of hiding the higher-order leakages in hardware. What are the achievements versus overheads?
• Protecting triple-DES against DPA. A practical application of domain-oriented masking

Uses Software

• PRESENT

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