scientific article; zbMATH DE number 2079921
zbMATH Open1045.68563MaRDI QIDQ4472066FDOQ4472066
Authors: Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger 
Publication date: 3 August 2004
Full work available at URL: http://link.springer.de/link/service/series/0558/bibs/2271/22710067.htm
Title of this publication is not available (Why is that?)
Recommendations
scalabilityinversionpipeliningadvanced encryption standardfinite field arithmeticvery large scale integrationstandard-cell designapplication specific integrated circuit
Data encryption (aspects in computer science) (68P25) Cryptography (94A60) Algebraic coding theory; cryptography (number-theoretic aspects) (11T71) Analytic circuit theory (94C05)
Cited In (17)
- A Very Compact S-Box for AES
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- Architectures and VLSI implementations of the AES-Proposal Rijndael
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- S-box pipelining using genetic algorithms for high-throughput AES implementations: how fast can we go?
- Practical Attacks on Masked Hardware
- Extreme pipelining towards the best area-performance trade-off in hardware
- A Very Compact “Perfectly Masked” S-Box for AES
- Design of fault-resilient S-boxes for AES-like block ciphers
- Using Normal Bases for Compact Hardware Implementations of the AES S-Box
- Logic minimization techniques with applications to cryptology
- Title not available (Why is that?)
- Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs
- Very Short Critical Path Implementation of AES with Direct Logic Gates
- Topics in Cryptology – CT-RSA 2005
- AES side-channel countermeasure using random tower field constructions
- Secure hardware implementation of nonlinear functions in the presence of glitches
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