An optimized S-Box circuit architecture for low power AES design

DOI10.1007/3-540-36400-5_14MaRDI QIDQ4425698zbMATH OpenFDO

Authors Sumio Morioka, Akashi Satoh

Publication date 11 September 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2523/25230172.htm

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

Recommendations

• An ASIC implementation of the AES S-boxes
• On the construction of hardware-friendly \(4\times4\) and \(5\times5\) S-boxes
• A Very Compact S-Box for AES
• A compact Rijndael hardware architecture with S-Box optimization
• SCA-resistance for AES: how cheap can we go?

Cited in

(6)

• On the construction of hardware-friendly \(4\times4\) and \(5\times5\) S-boxes
• Logic minimization techniques with applications to cryptology
• A Very Compact “Perfectly Masked” S-Box for AES
• Vortex: A New Family of One-Way Hash Functions Based on AES Rounds and Carry-Less Multiplication
• Construction of \(\mathrm{S}_8\) Liu J S-boxes and their applications
• AES side-channel countermeasure using random tower field constructions

This page was built for publication: An optimized S-Box circuit architecture for low power AES design

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4425698)