A comparative study of performance of AES final candidates using FPGAs

DOI10.1007/3-540-44499-8_9MaRDI QIDQ4536214zbMATH OpenFDO

Authors Andreas Dandalis, José Rolim, V. K. Prasanna Kumar

Publication date 28 November 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/3-540-44499-8_9

zbMATH Keywords

encryptionfield programmable gate arrayskey-setup latencyprivate-key cryptographythroughput

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Computing methodologies and applications (68U99) Cryptography (94A60)

Recommendations

• Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays
• Advanced Encryption Standard – AES
• AES implementation on FPGA: Time-flexibility tradeoff
• Looting the LUTs: FPGA optimization of AES and AES-like ciphers for authenticated encryption
• Implementation of the AES-128 on Virtex-5 FPGAs
• Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs
• AES on FPGA from the Fastest to the Smallest

Cited in

(5)

• 64-bit block ciphers: hardware implementations and comparison analysis
• Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays
• scientific article; zbMATH DE number 6501605 (Why is no real title available?)
• AES implementation on FPGA: Time-flexibility tradeoff
• Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs

Describes a project that uses

Uses Software

• Twofish

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