DOI10.2478/s13537-013-0112-2zbMath1409.94902MaRDI QIDQ469056
J. Herrera, Sumit K. Garg
Publication date: 10 November 2014 Published in: Central European Journal of Computer Science (Search for Journal in Brave) Full work available at URL: https://doi.org/10.2478/s13537-013-0112-2
zbMATH Keywords
cryptography; FPGA; throughput; AES; ASIC; parallel sub-pipelined
Mathematics Subject Classification ID
94A60: Cryptography