PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC (Q469056)
From MaRDI portal
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC |
scientific article |
Statements
PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC (English)
0 references
10 November 2014
0 references
cryptography
0 references
AES
0 references
FPGA
0 references
ASIC
0 references
parallel sub-pipelined
0 references
throughput
0 references
