PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC (Q469056)
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scientific article; zbMATH DE number 6367282
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| English | PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC |
scientific article; zbMATH DE number 6367282 |
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PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC (English)
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10 November 2014
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cryptography
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AES
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FPGA
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ASIC
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parallel sub-pipelined
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throughput
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0.86896837
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0.86623806
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0.8436806
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