Two methods of Rijndael implementation in reconfigurable hardware

DOI10.1007/3-540-44709-1_8MaRDI QIDQ4797786zbMATH OpenFDO

Authors Viktor Fischer, Miloš Drutarovský

Publication date 9 March 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2162/21620077

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Computing methodologies and applications (68U99) Cryptography (94A60)

Recommendations

• Efficient Implementations of Some Tweakable Enciphering Schemes in Reconfigurable Hardware
• Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes
• Architectures and VLSI implementations of the AES-Proposal Rijndael
• scientific article; zbMATH DE number 1979281
• scientific article; zbMATH DE number 2081069
• Topics in Cryptology – CT-RSA 2005
• Topics in Cryptology – CT-RSA 2004

Cited in

(11)

• Rijndael FPGA implementations utilising look-up tables
• Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays
• Dynamically reconfigurable encryption system of the AES
• scientific article; zbMATH DE number 1941129 (Why is no real title available?)
• scientific article; zbMATH DE number 1979281 (Why is no real title available?)
• scientific article; zbMATH DE number 1979282 (Why is no real title available?)
• Architectures and VLSI implementations of the AES-Proposal Rijndael
• JBits\(^{TM}\) implementations of the advanced encryption standard (Rijndael)
• High performance single-chip FPGA Rijndael algorithm implementations
• Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes
• Resource efficient implementation of T-boxes in AES on virtex-5 FPGA

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