A fault-tolerant hexagonal systolic array (Q1198057): Difference between revisions

A concurrent error detecting systolic design and algorithm is presented for band matrix multiplication on a hexagonal systolic array, that uses fewer comparators than Choi's design [\textit{Y. H. Choi}, Systolic diagnosis of processor arrays, Ph.D. Thesis, The University of Texas at Austin (1986)]. An error correcting design is also presented that performs computations in triplicate by utilizing the property that in any row or column of the systolic array, out of every three consecutive PE's, only is active at any given time.