A nonlinear optimization methodology for VLSI fixed-outline floorplanning (Q1016045): Difference between revisions

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Property / full work available at URL: https://doi.org/10.1007/s10878-008-9148-y / rank
 
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Latest revision as of 12:29, 1 July 2024

scientific article
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A nonlinear optimization methodology for VLSI fixed-outline floorplanning
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    A nonlinear optimization methodology for VLSI fixed-outline floorplanning (English)
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    4 May 2009
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    circuit layout design
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    VLSI floorplanning
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    facility layout
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    combinatorial optimization
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    global optimization
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    convex programming
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