A nonlinear optimization methodology for VLSI fixed-outline floorplanning

DOI10.1007/s10878-008-9148-yzbMath1163.90715OpenAlexW1978440339MaRDI QIDQ1016045

Chaomin Luo, Anthony Vannelli, Miguel F. Anjos

Publication date: 4 May 2009

Published in: Journal of Combinatorial Optimization (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10878-008-9148-y

zbMATH Keywords

global optimizationcombinatorial optimizationconvex programmingfacility layoutVLSI floorplanningcircuit layout design

Mathematics Subject Classification ID

Convex programming (90C25) Combinatorial optimization (90C27)

Related Items (5)

Strong mixed-integer formulations for the floor layout problem ⋮ Beating the SDP bound for the floor layout problem: a simple combinatorial idea ⋮ An improved two-stage optimization-based framework for unequal-areas facility layout ⋮ Mathematical optimization approach for facility layout on several rows ⋮ Global Approaches for Facility Layout and VLSI Floorplanning

Uses Software

• AMPL
• MINOS
• NEOS
• PATOMA

Cites Work

• A Modeling Language for Mathematical Programming
• Floorplan design of VLSI circuits
• An attractor-repeller approach to floorplanning
• A New Mathematical-Programming Framework for Facility-Layout Design
• Floorplans, planar graphs, and layouts
• Optimal module sizing in VLSI floorplanning by nonlinear programming
• Two-dimensional stochastic model for interconnections in master slice integrated circuits
• A projected Lagrangian algorithm and its implementation for sparse nonlinear constraints
• Large-scale linearly constrained optimization
• Semidefinite Programming

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