Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench (Q1029101): Difference between revisions
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Property / describes a project that uses: Concurrency Workbench / rank | |||
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Property / full work available at URL: https://doi.org/10.1016/j.ipl.2003.12.007 / rank | |||
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Property / OpenAlex ID: W2093834030 / rank | |||
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Property / cites work: Handshake Circuits / rank | |||
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Property / cites work: Q3997501 / rank | |||
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Property / cites work: Q3777424 / rank | |||
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Property / cites work: Receptive process theory / rank | |||
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Property / cites work: Q3992568 / rank | |||
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Latest revision as of 19:04, 1 July 2024
scientific article
Language | Label | Description | Also known as |
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English | Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench |
scientific article |
Statements
Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench (English)
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9 July 2009
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formal methods
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specification languages
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formal verification
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asynchronous logic
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