Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench

DOI10.1016/J.IPL.2003.12.007MaRDI QIDQ1029101zbMATH OpenOpenAlexFDO

Authors Hemangee K. Kapoor, Mark B. Josephs

Publication date 9 July 2009

Published in Information Processing Letters (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.ipl.2003.12.007

zbMATH Keywords

asynchronous logicformal methodsformal verificationspecification languages

Mathematics Subject Classification ID

Abstract data types; algebraic specification (68Q65)

Recommendations

• On process-algebraic verification of asynchronous circuits
• scientific article; zbMATH DE number 1303725
• Controllable delay-insensitive processes
• A formal approach to designing delay-insensitive circuits
• scientific article; zbMATH DE number 177530

Cites work

• Handshake Circuits
• scientific article; zbMATH DE number 4039251 (Why is no real title available?)
• scientific article; zbMATH DE number 42752 (Why is no real title available?)
• scientific article; zbMATH DE number 48630 (Why is no real title available?)
• scientific article; zbMATH DE number 559729 (Why is no real title available?)
• scientific article; zbMATH DE number 1438577 (Why is no real title available?)
• Receptive process theory
• Trace theory and VLSI design

Cited in

(7)

• On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP
• Delay-time modelling and critical-path verification for CMOS digital designs
• scientific article; zbMATH DE number 177530 (Why is no real title available?)
• scientific article; zbMATH DE number 1515325 (Why is no real title available?)
• Diagrammatic reasoning for delay-insensitive asynchronous circuits
• PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog
• scientific article; zbMATH DE number 5042670 (Why is no real title available?)

Describes a project that uses

Uses Software

• Concurrency Workbench

This page was built for publication: Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1029101)