Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench (Q1029101)
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scientific article; zbMATH DE number 5576956
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| English | Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench |
scientific article; zbMATH DE number 5576956 |
Statements
Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench (English)
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9 July 2009
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formal methods
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specification languages
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formal verification
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asynchronous logic
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0.778525173664093
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0.7722654342651367
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0.7715376615524292
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