Handshake Circuits

DOI10.1017/CBO9780511585777MaRDI QIDQ4321781zbMATH OpenOpenAlexFDO

Authors Kees van Berkel

Publication date 29 January 1995

Full work available at URL https://doi.org/10.1017/cbo9780511585777

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Analytic circuit theory (94C05)

Cited in

(11)

• On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP
• Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench
• STG decomposition strategies in combination with unfolding
• Verified compilation of communicating processes into clocked circuits
• Delay-insensitivity and ternary simulation
• Retargeting a hardware compiler using protocol converters
• Structure-based deadlock checking of asynchronous circuits
• Proof producing synthesis of arithmetic and cryptographic hardware
• Handshake games
• The Calculus of Handshake Configurations
• A Petri Net Model of Handshake Protocols

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