Delay-insensitivity and ternary simulation

DOI10.1016/S0304-3975(99)00273-XzbMath0946.68005MaRDI QIDQ1575731

Janusz A. Brzozowski

Publication date: 21 August 2000

Published in: Theoretical Computer Science (Search for Journal in Brave)

zbMATH Keywords

networkcircuitasynchronousternary simulationternary algebrafundamental modesemi-modulardelay-insensitivegeneral multiple-winnerinput-output modespeed-independent

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computer system organization (68M99)

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Cites Work

• Receptive process theory
• On the existence of speed-independent circuits
• A formal approach to designing delay-insensitive circuits
• On the existence of delay-insensitive fair arbiters: Trace theory and its limitations
• Trace theory and VLSI design
• A new explanation of the glitch phenomenon
• Automata Studies. (AM-34)
• A Characterization of Ternary Simulation of Gate Networks
• On a Ternary Model of Gate Networks
• Handshake Circuits
• Generalized ternary simulation of sequential circuits
• Hazard Detection in Combinational and Sequential Switching Circuits
• On the delay-sensitivity of gate networks
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