Generalized ternary simulation of sequential circuits

DOI10.1051/ita/1994283-401591zbMath0879.94040OpenAlexW128659725MaRDI QIDQ4365005

Carl-Johan H. Seger, Janusz A. Brzozowski

Publication date: 30 October 1997

Published in: RAIRO - Theoretical Informatics and Applications (Search for Journal in Brave)

Full work available at URL: https://eudml.org/doc/92473

zbMATH Keywords

ternary simulationgeneral multiple-winnerasynchronous gate circuitsGMW analysis

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

Related Items (6)

Cyclic Boolean circuits ⋮ Formal Reasoning About Causality Analysis ⋮ Gate circuits in the algebra of transients ⋮ Delay-insensitivity and ternary simulation ⋮ Verification of Asynchronous Circuits using Timed Automata ⋮ Product interval automata

Cites Work

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• A new explanation of the glitch phenomenon
• A Characterization of Ternary Simulation of Gate Networks
• On a Ternary Model of Gate Networks
• Hazard Detection in Combinational and Sequential Switching Circuits
• On the delay-sensitivity of gate networks
• Application of Ternary Algebra to the Study of Static Hazards

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