scientific article; zbMATH DE number 8771

zbMATH Open0747.94024MaRDI QIDQ3971259FDOQ3971259

Authors: Carl-Johan H. Seger, Janusz Brzozowski 

Publication date: 25 June 1992

Title of this publication is not available (Why is that?)

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zbMATH Keywords

logic gatesdesign methodologyasynchronous circuitsbounded-delay modelscomplexity of asynchronous circuit analysisMOS switch-level models

Mathematics Subject Classification ID

Research exposition (monographs, survey articles) pertaining to information and communication theory (94-02) Complexity classes (hierarchies, relations among complexity classes, etc.) (68Q15)

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• Generalized ternary simulation of sequential circuits
• Hyperidentities and related concepts. II
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• Testing asynchronous circuits: A survey
• Denotational fixed-point semantics for constructive scheduling of synchronous concurrency
• Design automation of real life asynchronous devices and systems
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• An exercise in the automatic verification of asynchronous designs
• A unified framework for race analysis of asynchronous networks
• Automata of asynchronous behaviors
• Model Checking Real-Time Systems
• Constructive semantics for instantaneous reactions
• True concurrency in models of asynchronous circuit behavior
• An inverse method for parametric timed automata
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• Models of asynchronous logical circuits and delays

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