Modular asynchronous arbiter insensitive to metastability

DOI10.1109/12.477251MaRDI QIDQ4421139zbMATH OpenOpenAlexFDO

Authors M. València, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, S. Sánchez-Solano

Publication date 1995

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.477251

zbMATH Keywords

asynchronous circuitsmodular designQ-flop resolver

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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