On a Ternary Model of Gate Networks

DOI10.1109/TC.1979.1675317zbMATH Open0408.94023OpenAlexW1983253480MaRDI QIDQ4196352FDOQ4196352

Authors: Michael Yoeli, Janusz Brzozowski 

Publication date: 1979

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1979.1675317

zbMATH Keywords

HazardAsynchronous NetworkBinary Sequential Gate NetworksGeneral Multiple WinnerOszillationRaceTernary Model

Mathematics Subject Classification ID

Cited In (6)

• An optimistic ternary simulation of gate races
• Generalized ternary simulation of sequential circuits
• Constructive Boolean circuits and the exactness of timed ternary simulation
• Gate circuits in the algebra of transients
• On the existence of speed-independent circuits
• Delay-insensitivity and ternary simulation

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