Constructive Boolean circuits and the exactness of timed ternary simulation

DOI10.1007/s10703-012-0144-6zbMath1303.94148OpenAlexW1978909743MaRDI QIDQ453539

Thomas R. Shiple, Gérard Berry, Michael Mendler

Publication date: 27 September 2012

Published in: Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10703-012-0144-6

zbMATH Keywords

constructive logiccombinational circuitsdelay modelsternary simulation

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Related Items (3)

Constructive semantics for instantaneous reactions ⋮ Constructive Boolean circuits and the exactness of timed ternary simulation ⋮ Denotational fixed-point semantics for constructive scheduling of synchronous concurrency

Uses Software

• Esterel

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