An optimistic ternary simulation of gate races

DOI10.1016/0304-3975(88)90107-7MaRDI QIDQ1106812zbMATH OpenOpenAlexFDO

Authors Carl-Johan H. Seger, Janusz Brzozowski

Publication date 1988

Published in Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0304-3975(88)90107-7

zbMATH Keywords

binary almost- equal-delay modelbinary race analysisconsiderable importancecritical races and hazardsternary modeltiming problems in digital networks

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

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Cites work

• A Characterization of Ternary Simulation of Gate Networks
• A Switch-Level Model and Simulator for MOS Digital Systems
• Hazard Detection in Combinational and Sequential Switching Circuits
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• scientific article; zbMATH DE number 3959288 (Why is no real title available?)
• scientific article; zbMATH DE number 3483927 (Why is no real title available?)
• On a Ternary Model of Gate Networks

Cited in

(8)

• Racing conditions in analog combinational circuits composed of adders and multipliers
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• scientific article; zbMATH DE number 3956984 (Why is no real title available?)
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• A unified framework for race analysis of asynchronous networks
• Generalized ternary simulation of sequential circuits
• Constructive Boolean circuits and the exactness of timed ternary simulation

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