A formal approach to designing delay-insensitive circuits

DOI10.1007/BF02252954MaRDI QIDQ808286zbMATH OpenFDO

Authors Jo C. Ebergen

Publication date 1991

Published in Distributed Computing (Search for Journal in Brave)

zbMATH Keywords

regular expressionsasynchronous circuittrace semanticscommunication behaviordelay- insensitive circuits

Mathematics Subject Classification ID

Circuits, networks (94C99) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

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• Communicating sequential processes
• Compiling communicating processes into delay-insensitive VLSI circuits
• Trace theory and VLSI design

Cited in

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• Asynchronous datapaths and the design of an asynchronous adder
• A scheduling strategy for synchronous elastic designs
• scientific article; zbMATH DE number 1955905 (Why is no real title available?)
• Reconciling fault-tolerant distributed computing and systems-on-chip
• The asynchronous bounded-cycle model
• scientific article; zbMATH DE number 177530 (Why is no real title available?)
• Direction-reversible self-timed cellular automata for delay-insensitive circuits
• Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench
• Delay-insensitive gate-level pipelining
• Controllable delay-insensitive processes
• scientific article; zbMATH DE number 139980 (Why is no real title available?)
• Compiling communicating processes into delay-insensitive VLSI circuits
• scientific article; zbMATH DE number 2102700 (Why is no real title available?)
• scientific article; zbMATH DE number 177245 (Why is no real title available?)
• Arbitration and reversibility of parallel delay-insensitive modules
• A theory of electrical circuits with resistively coupled distributed structures: delay time predicting
• scientific article; zbMATH DE number 108492 (Why is no real title available?)
• Delay-time modelling and critical-path verification for CMOS digital designs
• The Theta-Model: achieving synchrony without clocks
• scientific article; zbMATH DE number 139967 (Why is no real title available?)
• Diagrammatic reasoning for delay-insensitive asynchronous circuits
• scientific article; zbMATH DE number 194039 (Why is no real title available?)
• Delay-insensitivity and ternary simulation
• scientific article; zbMATH DE number 3869222 (Why is no real title available?)
• Synthesis of delay-verifiable combinational circuits

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