A formal approach to designing delay-insensitive circuits
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Publication:808286
DOI10.1007/BF02252954zbMATH Open0731.68081MaRDI QIDQ808286FDOQ808286
Authors: Jo C. Ebergen 
Publication date: 1991
Published in: Distributed Computing (Search for Journal in Brave)
Recommendations
regular expressionsasynchronous circuittrace semanticscommunication behaviordelay- insensitive circuits
Circuits, networks (94C99) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)
Cites Work
Cited In (22)
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- Diagrammatic Reasoning for Delay-Insensitive Asynchronous Circuits
- The asynchronous bounded-cycle model
- Delay-insensitive gate-level pipelining
- Controllable delay-insensitive processes
- Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench
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- Compiling communicating processes into delay-insensitive VLSI circuits
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- A theory of electrical circuits with resistively coupled distributed structures: delay time predicting
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- The Theta-Model: achieving synchrony without clocks
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- Delay-time modelling and critical-path verification for CMOS digital designs
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- Delay-insensitivity and ternary simulation
- Title not available (Why is that?)
- Synthesis of delay-verifiable combinational circuits
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