Synthesis of delay-verifiable combinational circuits

DOI10.1109/12.364533zbMATH Open1040.68522OpenAlexW2121799587MaRDI QIDQ4419633FDOQ4419633

Authors: Wuudiann Ke, Premachandran R. Menon 

Publication date: 1995

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.364533

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zbMATH Keywords

delay-verifiabilitypath-delay faults

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cited In (6)

• Title not available (Why is that?)
• Synthesis of delay fault testability circuits
• Design for delay verifiability
• On the number of tests to detect all path delay faults in combinational logic circuits
• Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs
• Title not available (Why is that?)

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