On the number of tests to detect all path delay faults in combinational logic circuits

DOI10.1109/12.481486MaRDI QIDQ4420908zbMATH OpenOpenAlexFDO

Authors Irith Pomeranz, Sudhakar M. Reddy

Publication date 1996

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.481486

zbMATH Keywords

pipeliningresynthesis

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12)

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• Generation of high quality tests for robustly untestable path delay faults
• A simulator for at-speed robust testing of path delay faults in combinational circuits
• Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits
• Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method
• Path delay fault test design for circuits obtained by covering ROBDDs with CLBs

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