Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits
From MaRDI portal
Recommendations
- Constructing a sequence detecting robustly testable path delay faults in sequential circuits
- Path delay fault test design for circuits obtained by covering ROBDDs with CLBs
- On the number of tests to detect all path delay faults in combinational logic circuits
- Test generation for path delay faults using binary decision diagrams
- A simulator for at-speed robust testing of path delay faults in combinational circuits
Cites work
Cited in
(10)- Constructing a sequence detecting robustly testable path delay faults in sequential circuits
- Testing cross-talk induced delay faults in digital circuit based on transient current analysis
- Delay fault models for VLSI circuits
- scientific article; zbMATH DE number 1941112 (Why is no real title available?)
- Test generation for path delay faults using binary decision diagrams
- Generation of high quality tests for robustly untestable path delay faults
- A simulator for at-speed robust testing of path delay faults in combinational circuits
- On the number of tests to detect all path delay faults in combinational logic circuits
- Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs
- Path delay fault test design for circuits obtained by covering ROBDDs with CLBs
This page was built for publication: Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q500124)
