Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits
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Recommendations
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Cites work
Cited in
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- scientific article; zbMATH DE number 1941112 (Why is no real title available?)
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- Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs
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- Path delay fault test design for circuits obtained by covering ROBDDs with CLBs
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