Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits
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Publication:500124
DOI10.1134/S0005117915040104zbMATH Open1327.94093MaRDI QIDQ500124FDOQ500124
Authors: A. Yu. Matrosova, V. B. Lipskii 
Publication date: 1 October 2015
Published in: Automation and Remote Control (Search for Journal in Brave)
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Cites Work
Cited In (9)
- Testing cross-talk induced delay faults in digital circuit based on transient current analysis
- A simulator for at-speed robust testing of path delay faults in combinational circuits
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- On the number of tests to detect all path delay faults in combinational logic circuits
- Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs
- Generation of high quality tests for robustly untestable path delay faults
- Constructing a sequence detecting robustly testable path delay faults in sequential circuits
- Path delay fault test design for circuits obtained by covering ROBDDs with CLBs
- Test generation for path delay faults using binary decision diagrams
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