Generation of high quality tests for robustly untestable path delay faults

DOI10.1109/12.545968MaRDI QIDQ4420784zbMATH OpenOpenAlexFDO

Authors Kwang-Ting Cheng, Angela Krstic, Hsi-Chuan Chen

Publication date 1996

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://semanticscholar.org/paper/c12dd401d6bcb33f9bad1d9f4d185931677fc7b1

zbMATH Keywords

automatic test generationVLSI testingdelay testingtiming defects

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Recommendations

• A simulator for at-speed robust testing of path delay faults in combinational circuits
• Test generation for path delay faults using binary decision diagrams
• Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits
• On the number of tests to detect all path delay faults in combinational logic circuits
• Path delay fault test design for circuits obtained by covering ROBDDs with CLBs

Cited in

(3)

• A simulator for at-speed robust testing of path delay faults in combinational circuits
• A Practical Approach to Fault Simulation and Test Generation for Bridging Faults
• Constructing a sequence detecting robustly testable path delay faults in sequential circuits

This page was built for publication: Generation of high quality tests for robustly untestable path delay faults

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4420784)