| Publication | Date of Publication | Type |
|---|
On symmetric error correcting and all unidirectional error detecting codes
IEEE Transactions on Computers | 2018-09-14 | Paper |
A storage-based built-in test pattern generation method for scan circuits based on partitioning and reduction of a precomputed test set
IEEE Transactions on Computers | 2018-07-09 | Paper |
Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis
IEEE Transactions on Computers | 2017-07-27 | Paper |
Vertex splitting in dags and applications to partial scan designs and lossy circuits
International Journal of Foundations of Computer Science | 2015-04-29 | Paper |
Thread-parallel integrated test pattern generator utilizing satisfiability analysis
International Journal of Parallel Programming | 2010-08-13 | Paper |
INCREDYBLE: A new search strategy for design automation problems with applications to testing
IEEE Transactions on Computers | 2003-10-14 | Paper |
Delay fault models for VLSI circuits
Integration | 1999-01-12 | Paper |
On the number of tests to detect all path delay faults in combinational logic circuits
IEEE Transactions on Computers | 1996-01-01 | Paper |
On removing redundancies from synchronous sequential circuits with synchronizing sequences
IEEE Transactions on Computers | 1996-01-01 | Paper |
On fault simulation for synchronous sequential circuits
IEEE Transactions on Computers | 1995-01-01 | Paper |
Deleting vertices to bound path length
IEEE Transactions on Computers | 1994-01-01 | Paper |
On the role of hardware reset in synchronous sequential circuit test generation
IEEE Transactions on Computers | 1994-01-01 | Paper |
On self-fault diagnosis of the distributed systems
IEEE Transactions on Computers | 1988-01-01 | Paper |
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers | 1987-01-01 | Paper |
Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
IEEE Transactions on Computers | 1986-01-01 | Paper |
A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair
IEEE Transactions on Computers | 1984-01-01 | Paper |
A Fault-Tolerant Communication Architecture for Distributed Systems
IEEE Transactions on Computers | 1982-01-01 | Paper |
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers | 1980-01-01 | Paper |
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
IEEE Transactions on Computers | 1978-01-01 | Paper |
A Multicode Single Transition-Time State Assignment for Asynchronous Sequential Machines
IEEE Transactions on Computers | 1978-01-01 | Paper |
On Totally Self-Checking Checkers for Separable Codes
IEEE Transactions on Computers | 1977-01-01 | Paper |
A Note on Testing Logic Circuits by Transition Counting
IEEE Transactions on Computers | 1977-01-01 | Paper |
Comments on "Minimal Fault Tests for Combinational Networks"
IEEE Transactions on Computers | 1977-01-01 | Paper |
Techniques to Construct (2,1) Separating Systems from Linear Error-Correcting Codes
IEEE Transactions on Computers | 1976-01-01 | Paper |
On Minimally Testable Logic Networks
IEEE Transactions on Computers | 1974-01-01 | Paper |
Note on Self-Checking Checkers
IEEE Transactions on Computers | 1974-01-01 | Paper |
Further results on decoders for<tex>Q</tex>-ary output channels (Corresp.)
IEEE Transactions on Information Theory | 1974-01-01 | Paper |
On the Design of Logic Networks with Redundancy and Testability Considerations
IEEE Transactions on Computers | 1974-01-01 | Paper |
Easily Testable Two-Dimensional Cellular Logic Arrays
IEEE Transactions on Computers | 1974-01-01 | Paper |
Design of Two-Level Fault-Tolerant Networks
IEEE Transactions on Computers | 1974-01-01 | Paper |
Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions
IEEE Transactions on Computers | 1974-01-01 | Paper |
| scientific article; zbMATH DE number 3559467 (Why is no real title available?) | 1973-01-01 | Paper |
A (48, 31, 8) linear code (Corresp.)
IEEE Transactions on Information Theory | 1973-01-01 | Paper |
Complete Test Sets for Logic Functions
IEEE Transactions on Computers | 1973-01-01 | Paper |
Fault-Tolerant Asynchronous Networks
IEEE Transactions on Computers | 1973-01-01 | Paper |
Easily Testable Realizations ror Logic Functions
IEEE Transactions on Computers | 1972-01-01 | Paper |
New binary codes
IEEE Transactions on Information Theory | 1972-01-01 | Paper |
Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers | 1972-01-01 | Paper |
Random error and burst correction by iterated codes
IEEE Transactions on Information Theory | 1972-01-01 | Paper |
On block codes with specified maximum distance (Corresp.)
IEEE Transactions on Information Theory | 1972-01-01 | Paper |
Hybrid block- self-orthogonal convolutional codes
IEEE Transactions on Information Theory | 1972-01-01 | Paper |
Linear convolutional codes for compound channels
Information and Control | 1972-01-01 | Paper |
Forward-error correction with decision feedback
Information and Control | 1972-01-01 | Paper |
Error-Control Techniques for Logic Processors
IEEE Transactions on Computers | 1972-01-01 | Paper |
A Design Procedure for Fault-Locatable Switching Circuits
IEEE Transactions on Computers | 1972-01-01 | Paper |
Circulant bases for cyclic codes (Corresp.)
IEEE Transactions on Information Theory | 1970-01-01 | Paper |
On decoding iterated codes
IEEE Transactions on Information Theory | 1970-01-01 | Paper |
A class of high-rate double-error-correcting convolutional codes
Information and Control | 1970-01-01 | Paper |
A note on decoding of block codes (Corresp.)
IEEE Transactions on Information Theory | 1969-01-01 | Paper |
A decoding algorithm for some convolutional codes constructed from block codes
Information and Control | 1968-01-01 | Paper |
A construction for convolutional codes using block codes
Information and Control | 1968-01-01 | Paper |
