On the role of hardware reset in synchronous sequential circuit test generation

DOI10.1109/12.312119zbMath1061.68511MaRDI QIDQ4419767

Irith Pomeranz, Sudhakar M. Reddy

Publication date: 1994

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.312119

zbMATH Keywords

hardware reset

Mathematics Subject Classification ID

94C12: Fault detection; testing in circuits and networks

68M15: Reliability, testing and fault tolerance of networks and computer systems

Uses Software

• HITEC