Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
From MaRDI portal
Publication:3716977
DOI10.1109/TC.1986.1676825zbMath0588.94019OpenAlexW2043905562MaRDI QIDQ3716977
Madhukar K. Reddy, Sudhakar M. Reddy
Publication date: 1986
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/tc.1986.1676825
Related Items
This page was built for publication: Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits