A storage-based built-in test pattern generation method for scan circuits based on partitioning and reduction of a precomputed test set
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Publication:4571243
DOI10.1109/TC.2002.1047753zbMath1391.94933MaRDI QIDQ4571243
Irith Pomeranz, Sudhakar M. Reddy
Publication date: 9 July 2018
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
94C12: Fault detection; testing in circuits and networks
