On Minimally Testable Logic Networks

DOI10.1109/T-C.1974.223981zbMATH Open0279.94032OpenAlexW2157061909MaRDI QIDQ4767239FDOQ4767239

K. K. Saluja, Sudhakar M. Reddy

Publication date: 1974

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/t-c.1974.223981

Mathematics Subject Classification ID

Cited In (6)

• Maximum ease of testability of logic circuits with respect to multiple stuck-on faults
• The length of a single fault detection test for constant-nonpreserving element insertions
• A method of synthesis of irredundant circuits admitting single fault detection tests of constant length
• Complete Fault Detection Tests of Length 2 for Logic Networks under Stuck-at Faults of Gates
• On the exact value of the length of the minimal single diagnostic test for a particular class of circuits
• Short Complete Fault Detection Tests for Logic Networks with Fan-In Two

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