On Minimally Testable Logic Networks
From MaRDI portal
Publication:4767239
DOI10.1109/T-C.1974.223981zbMath0279.94032OpenAlexW2157061909MaRDI QIDQ4767239
K. K. Saluja, Sudhakar M. Reddy
Publication date: 1974
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/t-c.1974.223981
Related Items
The length of a single fault detection test for constant-nonpreserving element insertions ⋮ Complete Fault Detection Tests of Length 2 for Logic Networks under Stuck-at Faults of Gates ⋮ On the exact value of the length of the minimal single diagnostic test for a particular class of circuits ⋮ A method of synthesis of irredundant circuits admitting single fault detection tests of constant length ⋮ Short Complete Fault Detection Tests for Logic Networks with Fan-In Two ⋮ Maximum ease of testability of logic circuits with respect to multiple stuck-on faults
This page was built for publication: On Minimally Testable Logic Networks
