scientific article; zbMATH DE number 139979

zbMATH Open0759.94022MaRDI QIDQ4028336FDOQ4028336

Authors: Scott F. Smith, Amy E. Zwarico 

Publication date: 28 March 1993

Title of this publication is not available (Why is that?)

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zbMATH Keywords

specificationcorrectness of specification ruleslarge asynchronous circuitspost hoc verification techniques

Mathematics Subject Classification ID

Modes of computation (nondeterministic, parallel, interactive, probabilistic, etc.) (68Q10) Fault detection; testing in circuits and networks (94C12)

Cited In (11)

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• Logic Synthesis for Asynchronous Controllers and Interfaces
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• Title not available (Why is that?)
• Title not available (Why is that?)
• Retargeting a hardware compiler using protocol converters
• An exercise in the automatic verification of asynchronous designs
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• Concurrent Rewriting Semantics and Analysis of Asynchronous Digital Circuits
• Synthesis of delay-verifiable combinational circuits

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