Specification of an asynchronous on-chip bus

DOI10.1007/3-540-36103-0_39MaRDI QIDQ4412520zbMATH OpenFDO

Authors Tiberiu Seceleanu, J. Plosila

Publication date 15 July 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2495/24950383.htm

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Computing methodologies and applications (68U99)

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Cited in

(3)

• A specification methodology by a collection of compact properties as applied to the Intel\(^\circledR\) Itanium\(^{\text{TM}}\) processor bus protocol
• Refinement-based formal verification of asynchronous wrappers for independently clocked domains in systems on chip
• Formal pipeline design

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