Verification of asynchronous circuits using timed automata

DOI10.1016/S1571-0661(04)80468-7MaRDI QIDQ2842571zbMATH OpenFDO

Authors Marius Bozga, Hou Jianmin, Oded Maler, Sergio Yovine

Publication date 15 August 2013

Published in Electronic Notes in Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/S1571-0661(04)80468-7

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60)

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Cites work

• A theory of timed automata
• Generalized ternary simulation of sequential circuits
• scientific article; zbMATH DE number 1304998 (Why is no real title available?)
• scientific article; zbMATH DE number 3273524 (Why is no real title available?)
• Timing verification by successive approximation
• Uppaal in a nutshell

Cited in

(14)

• Timed verification of the generic architecture of a memory circuit using parametric timed automata
• Automata of asynchronous behaviors
• Model Checking Real-Time Systems
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• Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
• RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking
• scientific article; zbMATH DE number 139802 (Why is no real title available?)
• scientific article; zbMATH DE number 139979 (Why is no real title available?)
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• SAT-based verification for timed component connectors
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• Computer Aided Verification

Describes a project that uses

Uses Software

• Uppaal
• Kronos
• Petrify

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