Petrify
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Cited in
(36)- Verification of asynchronous circuits using timed automata
- Checking timed Büchi automata emptiness efficiently
- Verification of asynchronous systems with an unspecified component
- scientific article; zbMATH DE number 2112981 (Why is no real title available?)
- STG decomposition strategies in combination with unfolding
- scientific article; zbMATH DE number 1955907 (Why is no real title available?)
- Applications and Theory of Petri Nets 2005
- scientific article; zbMATH DE number 5042671 (Why is no real title available?)
- scientific article; zbMATH DE number 1820087 (Why is no real title available?)
- Petri Net Synthesis for Restricted Classes of Nets
- Resolution of encoding conflicts by signal insertion and concurrency reduction based on STG unfoldings
- Synthesising elementary net systems with localities
- Some Basic Techniques Allowing Petri Net Synthesis: Complexity and Algorithmic Issues
- CADRE: An asynchronous embedded DSP for mobile phone applications
- rbminer
- TRANSYT
- Workcraft
- Wendy
- ProM
- BPEL2oWFN
- Genet
- VipTool
- Synet
- APT
- Jacco
- Computer Aided Verification
- Balsa: An Asynchronous Hardware Synthesis Language
- A predictive synchronizer for periodic clock domains
- Bounded choice-free Petri net synthesis: algorithmic issues
- scientific article; zbMATH DE number 1955905 (Why is no real title available?)
- scientific article; zbMATH DE number 1955912 (Why is no real title available?)
- Compact representations and efficient algorithms for operating guidelines
- The power of prime cycles
- scientific article; zbMATH DE number 2112982 (Why is no real title available?)
- Distributed simulation of asynchronous Hardware: The program driven synchronization protocol
- Component refinement and CSC-solving for STG decomposition
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