Petrify

swMATH9784MaRDI QIDQ21763FDOQ21763

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Official website: http://www.lsi.upc.edu/~jordicf/petrify/

Cited In (33)

• Resolution of encoding conflicts by signal insertion and concurrency reduction based on STG unfoldings
• CADRE: An asynchronous embedded DSP for mobile phone applications
• Title not available (Why is that?)
• Title not available (Why is that?)
• Verification of asynchronous systems with an unspecified component
• Title not available (Why is that?)
• Title not available (Why is that?)
• Title not available (Why is that?)
• Computer Aided Verification
• Compact representations and efficient algorithms for operating guidelines
• Distributed simulation of asynchronous Hardware: The program driven synchronization protocol
• The power of prime cycles
• Petri Net Synthesis for Restricted Classes of Nets
• Title not available (Why is that?)
• Checking timed Büchi automata emptiness efficiently
• Bounded choice-free Petri net synthesis: algorithmic issues
• Applications and Theory of Petri Nets 2005
• TRANSYT
• ProM
• BPEL2oWFN
• Genet
• VipTool
• Component refinement and CSC-solving for STG decomposition
• Synet
• APT
• Jacco
• STG decomposition strategies in combination with unfolding
• A predictive synchronizer for periodic clock domains
• Verification of asynchronous circuits using timed automata
• Title not available (Why is that?)
• Synthesising elementary net systems with localities
• Some Basic Techniques Allowing Petri Net Synthesis: Complexity and Algorithmic Issues
• Balsa: An Asynchronous Hardware Synthesis Language

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