Balsa: An Asynchronous Hardware Synthesis Language

DOI10.1093/COMJNL/45.1.12MaRDI QIDQ4328963zbMATH OpenOpenAlexFDO

Authors Doug Edwards, Andrew Bardsley

Publication date 20 January 2003

Published in The Computer Journal (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1093/comjnl/45.1.12

Mathematics Subject Classification ID

Computer system organization (68M99) Computing methodologies and applications (68U99)

Cited in

(3)

• On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP
• STG decomposition strategies in combination with unfolding
• Structure-based deadlock checking of asynchronous circuits

Describes a project that uses

Uses Software

• Petrify

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